SEALSQ Subsidiary IC’Alps Advances QASIC Roadmap for Custom Quantum-Resistant ASICs

Post-quantum semiconductor and digital identity developer SEALSQ Corp (NASDAQ: LAES) has announced an engineering update on QASIC (Quantum-Resistant Application-Specific Integrated Circuit), its sovereign post-quantum ASIC platform developed through its French chip design subsidiary, IC’Alps.

The initiative embeds hardware-accelerated Post-Quantum Cryptography (PQC) directly into customer-owned, application-specific silicon architectures. The joint engineering track remains on schedule to deliver its first functional prototype in 2026.

Embedding Post-Quantum Security at the Silicon Level

Standard microcontrollers and classical Hardware Security Modules (HSMs) rely on public-key algorithms (such as RSA and ECC) vulnerable to quantum decryption. The QASIC framework combines SEALSQ’s post-quantum root-of-trust IP with IC’Alps’ mixed-signal and analog ASIC capabilities to support three target markets:

• Cybersecurity & Infrastructure: Secure microcontrollers, identity authentication engines, secure communications, data protection, and critical infrastructure HSMs.
• Medical & Healthcare Devices: Implantable devices, connected diagnostic equipment, patient monitors, and healthcare data security.
• Automotive Systems: Software-Defined Vehicles (SDVs), autonomous driving compute units, Vehicle-to-Everything (V2X) communications, secure Over-the-Air (OTA) updates, and telematics.