Simultaneous high-fidelity single-qubit gates in a spin qubit array

Quantum computing holds the potential to revolutionize fields from cryptography to materials discovery, but building scalable, fault-tolerant quantum processors remains a central challenge. Spin qubits in solid-state devices^1,2 are a leading platform candidate, with a compact footprint and compatibility with industrial semiconductor fabrication^3,4,5,6, offering a route towards scaling to the millions of qubits envisioned for fault-tolerant quantum computing architectures⁷.

For fault-tolerant quantum computing, gate fidelities must exceed the threshold set by quantum error correction protocols, such as the surface code⁸. While the requirement depends on the noise model, fidelities above 99.9% are widely targeted for practical fault-tolerant operation^9,10. In scalable quantum processors, control must extend beyond sequential single-qubit gates to the simultaneous operation of multiple qubits, because idle qubits dephase much faster than driven ones. In our silicon spin qubits, for example, driven coherence times are about \({T}_{2}^{R}\approx 100\,\mathrm{\mu s}\), while idle dephasing times are only \({T}_{2}^{* }\approx 10\,\mathrm{\mu s}\). This makes sequential operations impractical at scale because minimizing qubit idle times requires simultaneous control across many qubits. However, parallel qubit control typically degrades fidelities because of crosstalk. Such degradation has been observed not only in spin qubits^11,12,13 but also in superconducting systems, where mitigation strategies have been developed^14,15,16,17. In spin qubits, the problem is particularly severe: fidelities were recently reported to drop considerably from 99.95% to 99.5% under parallel operation of only two qubits in silicon/silicon-germanium devices, the same platform used in this work¹². The physical origin of this degradation has remained unclear^11,12,13. Addressing it is therefore essential for implementing large-scale error correction codes that require parallel gate execution.