QuantWare Says Scaling Quantum Power Hinges On Efficiency, Not Just Qubits

QuantWare aims to have its D-Line components available for building quantum computer readout chains by September 25, 2026, signaling a focused push toward practical scalability. The Dutch startup, backed by investment from Intel, asserts that increasing computational power hinges on efficiency, specifically compute per watt, rather than simply adding more qubits. QuantWare’s approach centers on its VIO architecture, designed to hyperscale both qubit designs and chips, addressing a critical bottleneck in quantum processor development. This strategy positions the TU Delft spinout as a key player in moving beyond theoretical quantum computing toward industrial applications.

QuantWare’s VIO Enables Hyperscale Qubit Chip Design

QuantWare’s silicon-based VIO architecture allows for fitting 10,000 qubits onto a single system, a feat reported on June 25, 2026, and signaling a departure from simply increasing qubit numbers toward maximizing computational power per watt. This approach directly addresses a core challenge in quantum computing, as scaling qubit count alone does not guarantee improved performance; efficient signal management is equally critical.

The VIO framework facilitates flexibility in qubit designs and enables modularity at both the chip and architectural levels. QuantWare’s foundry services, opened to external customers in February 2026, further lower barriers to quantum hardware development by reducing fabrication costs and complexity, allowing third parties to prototype and build superconducting quantum chips, accelerating innovation beyond QuantWare’s internal research and development.