Xanadu and AMD Launch Open-Source Backline Extension for PennyLane

Xanadu Quantum Technologies (NASDAQ/TSX: XNDU) and AMD (NASDAQ: AMD) have released Backline, an open-source heterogeneous compilation and execution framework connecting quantum processing units (QPUs) with classical hardware engines. Integrated into Xanadu’s PennyLane platform and its MLIR-based Catalyst compiler, Backline establishes Python-native, ultra-low-latency links across CPUs, GPUs, FPGAs, and SmartNICs. The software resolves the classical-quantum data bottleneck by providing direct microsecond-scale communication required for quantum error correction (QEC), high-speed optical network routing, and quantum sensing.

To execute real-time QEC before physical qubits decohere, Backline achieves end-to-end loop latencies under 3 microseconds (2.3 μs mean CPU loop, 4.4 μs mean GPU loop). Operating over Remote Direct Memory Access (RDMA) via RoCE v2 protocols, the system utilizes zero-copy user-space memory (libibverbs) to bypass Linux kernel context switches and main memory bottlenecks. This speed allows Python-based syndrome decoders to process quantum measurements from FPGA controllers and issue gate corrections within strict microsecond execution budgets.

Backline proves standard enterprise processors like AMD EPYC™ and Threadripper™ CPUs can handle single-digit microsecond feedback loops out of the box without requiring custom ASICs or vendor-locked control hardware. Development teams can prototype low-latency feedback routines on standard workstations before scaling to enterprise AMD Instinct™ GPUs (MI200/MI300) and AMD Versal™ VPK120 adaptive FPGAs. This hardware-agnostic architecture bypasses GPU supply constraints and specialized shared-memory server requirements.