Altera and Riverlane Partner on QEC Interfaces for Agilex FPGAs Following Post-Quantum Security Rollout

FPGA provider Altera (an Intel company) and quantum error correction (QEC) specialist Riverlane have announced a partnership to optimize real-time QEC data movement and low-latency control logic across Altera’s Agilex® FPGA portfolio. Under the agreement, Riverlane joined the Altera Solutions Acceleration Partner (ASAP) Program and validated its open-source QEC Interface (QECi) protocol on Altera Agilex 7 devices, establishing a standardized data-interchange framework between quantum control electronics and physical QEC decoders.

The technical integration addresses the microsecond latency constraints of fault-tolerant quantum computing by leveraging Agilex 7 F-Tile transceivers to route syndrome data between control stacks and decoder chips with deterministic timing. By publishing the open-source QECi reference design on GitHub, the partners provide QPU developers with a hardware-validated starting point for multi-qubit parallel processing and high-bandwidth readout across superconducting, trapped-ion, and silicon spin-qubit platforms. The collaboration also encompasses high-throughput Agilex 9 Direct RF FPGAs, which integrate direct digital-to-analog and analog-to-digital data converters operating up to 64 Gsps across a 36 GHz RF range.