IBM and Siemens Collaborate to Advance 3D Nanostack Transistors

Insider Brief

• IBM and Siemens are collaborating to advance IBM’s 3D nanostack transistor architecture, focusing on design, simulation, lithography and manufacturing preparation.
• IBM says the current 7-angstrom design uses vertically stacked, staggered nanosheet transistors and could improve chip density, energy efficiency, performance and SRAM scaling.
• The companies will develop virtual models and refine design and fabrication techniques to address manufacturing challenges and prepare future nanostack generations for production.

PRESS RELEASE — Today, IBM (NYSE: IBM), in collaboration with Siemens, announced new research aimed at advancing IBM’s nanostack architecture, a new transistor architecture unveiled by IBM earlier this year. The collaboration will bring together IBM’s leadership in semiconductor device innovation and Siemens’ expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack.

Nanostack is the industry’s first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors to pack more transistors onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also unlocks the use of different material combinations within each stacked layer to optimize performance and power efficiency of each transistor independent of the other. These innovations power substantial leaps in energy efficiency, performance, and SRAM scaling.