Quantinuum Demonstrates Helix Quantum Error Correction Architecture on Helios Hardware

Trapped-ion quantum computing developer Quantinuum (NASDAQ: QNT) has announced the experimental validation of its Helix quantum error correction (QEC) architecture on its 98-qubit commercial processor, Helios. Detailed in a published research paper, the demonstration validated a complete fault-tolerant stack—spanning protected logical memory, high-speed logical Clifford computation, and inter-code logical entanglement—outperforming unencoded physical baselines across all benchmarked operations without relying on postselection.

The Helix architecture is built on the [[20, 2, 6]] C4-Helix code, a concatenated symplectic double code that pairs a [[10, 2, 3]] twisted toric code with a [[4, 2, 2]] block code. By utilizing the reconfigurable 2D shuttling capabilities of Quantinuum’s Quantum Charge-Coupled Device (QCCD) architecture, the code implements non-planar torus topologies to deliver a 3.5× reduction in spatial qubit overhead compared to traditional rotated surface codes of equivalent distance. In a 20-round memory benchmark under active syndrome extraction and hardware-level leakage repumping, Helix achieved a world-record logical memory error rate of 4.6 × 10^-5 per logical qubit per cycle (9.3 × 10^-5 block logical error per round), which further dropped to 1.9 × 10^-5 with 0.5% forced-gap decoder postselection.