SEEQC Combines Chip-Based Processing With NVIDIA AI to Improve Quantum Error Correction

Insider Brief

• SEEQC reported simulation results showing that combining its chip-based pre-decoder with NVIDIA Ising reduced quantum error-correction decoding time and logical error rates by approximately 50% compared with using Ising alone.
• The architecture places specialized processing closer to the quantum processor to reduce data transfers and support faster communication with GPU-based computing systems.
• SEEQC plans to integrate the demonstrated components into a quantum processor connected to high-performance computing infrastructure and evaluate further improvements in error correction and scalability.

PRESS RELEASE — – SEEQC, Inc. (“SEEQC” or the “Company”),a chip-based quantum computing company, today announced results demonstrating significant performance improvements in quantum error correction decoding through a digital interface optimized multi-stage decoding architecture combining SEEQC’s chip-based pre-decoder technology with the NVIDIA Ising open family of AI models.

SEEQC’s chip-based pre-decoder was integrated in a simulated quantum processor and architecture stack incorporating realistic decoder latency at scale, as a backend to NVIDIA Ising Decoding with SEEQC Digital Link and NVIDIA NVQLink providing the framework for low-latency communication between quantum and GPU-accelerated compute environments. Compared with operating NVIDIA Ising as a standalone pre-decoder, the combined multi-stage pre-decoder architecture demonstrated an approximately 50% reduction in decoding latency and logical error rate performance, the two key metrics that dictate the scalability of a fault tolerant quantum system. The overheads associated with error correction are enormous and can increase exponentially as systems scale towards useful computation. Therefore, a 50% improvement in these key scaling bottleneck metrics have a significant impact on the overall scalability and efficiency of a quantum processor.